Open role FPGA & RTL Design and Verification Engineer Our mission AI is becoming fundamental to how the world works. When it is, the ability to compute, and to manufacture the hardware that computes, should not be concentrated in a few places. Touchdown's mission is to make compute accessible to the whole world and to reindustrialize advanced semiconductor manufacturing in the United States. We co-design everything for next-generation compute: the AI systems people use, the software that serves them, the architectures and chips underneath, and the packaging, test, and manufacturing that make them real. Co-design brings down the complexity and cost of building compute. That is what makes manufacturing in America competitive again, and what puts compute within reach of people and companies everywhere. We build alongside the world's best manufacturing ecosystems, including Taiwan's, and every role here makes one layer better and carries what it learns to the rest. Why this role matters Ideas become credible when they run on real hardware. FPGA and RTL prototypes turn architecture concepts into measured results quickly. Technical scope RTL design in SystemVerilog or VHDL; verification with UVM or cocotb; FPGA synthesis, implementation, and timing closure; high-speed interfaces such as PCIe and memory; drivers and host integration; lab bring-up and measurement. First 90 days
• Take ownership of prototype bring-up.
• Implement and verify blocks against their models.
• Report measured results. What you will own




• RTL design and verification.
• FPGA implementation and timing closure.
• Drivers and host integration. What you bring
• SystemVerilog or VHDL design and verification.
• FPGA timing closure.
• Linux driver or host-integration experience.
• Has taken RTL from specification through verification to working hardware.
• Has closed timing on large FPGA designs. Helpful experience
• PCIe and DMA How we work
• AI-native by default. You use coding agents, AI-assisted analysis, and automation every day, and you check their output against measurements before anyone relies on it.
• We work alongside foundries, test houses, OSATs, and research labs, and we build with partners rather than against them. How the role works
• Full time.
•

Location:
Santa Clara, CA
• Hsinchu, Taiwan.
• Openings: 1–2.
• Taiwan roles are employed through a local employer of record. Mandarin is a strong plus for Taiwan roles; English is required for written work.
• Pay: $150,000–$200,000 base (Santa Clara, CA).
• Ranges are base pay for U.
S. roles and depend on location, experience, and level. Full-time roles also include equity and benefits. Taiwan pay is set to the local market and discussed in the first call.
• Start date and employment details are discussed during the process. Apply for this role → Applications are reviewed against the work described here. We do not use a degree, title, or keyword list as a substitute for evidence.

📌 FPGA & RTL Design and Verification Engineer (Bakshi Ka Talab)
🏢 Touchdown Labs
📍 Bakshi Ka Talab