Company Description CoreIC Technologies is a trusted engineering partner specializing in Semiconductor, Embedded Systems, Digital Engineering, Data & AI, and Cloud & DevOps solutions. The company helps organizations accelerate innovation, scale engineering teams, and improve product delivery with strong focus on speed and quality. From advanced chip design to cloud-native platforms, CoreIC Technologies brings deep domain expertise and execution excellence to every engagement. The team steps in when engineering groups are stretched, removing delivery bottlenecks, accelerating releases, and keeping critical programs on track. CoreIC’s broad portfolio includes semiconductor engineering, embedded product development, digital platforms, data and AI engineering, and quality and security services. Role Description This is a full time, on-site Senior Physical Design Engineer role based in Bangalore Urban. The role involves owning and executing physical design flows for complex ASIC/SoC projects, including floorplanning, placement, clock tree synthesis, routing, and timing closure. The engineer will collaborate closely with RTL, verification, and circuit design teams to ensure that performance, power, and area targets are met. Daily responsibilities include analyzing constraints, running physical verification, resolving DRC/LVS issues, and optimizing designs for manufacturability and reliability.



The role also includes contributing to methodology improvements, reviewing design specifications, mentoring junior engineers, and ensuring high-quality tape-out deliverables for customer programs. Qualifications
• Candidates should possess strong skills in Physical Design, including floorplanning, placement, CTS, routing, and timing closure.
• Candidates should possess skills in Physical Verification, including DRC, LVS, and sign-off checks using industry-standard tools.
• Candidates should possess skills in Logic Design and Circuit Design to understand design intent, constraints, and performance trade-offs.
• Candidates should possess skills in RTL Design, including familiarity with synthesizable RTL, constraints, and interaction with front-end flows.
• Relevant skills such as proficiency with EDA tools (e.g., Cadence, Synopsys, Mentor), static timing analysis, and power/IR-drop analysis are beneficial.
• A bachelor’s or master’s degree in Electrical Engineering, Electronics, or a related field, and significant experience in ASIC/SoC physical design are preferred.
• Strong analytical, communication, and collaboration abilities, along with willingness to mentor team members and work on-site with cross-functional teams, are important.

📌 Senior Physical Design Engineer (India)
🏢 CoreIC Technologies
📍 India