Job Description

Experience:
5-8 Years

Location:
Hyderabad Notice Period: < 30 days We are looking for candidates with strong Front-End implementation experience, particularly in Synthesis, Timing Closure, CDC, Lint, and DFT signoff activities. The role will primarily involve:
• Running and analyzing Synthesis, Lint, CDC, RDC, and DFT checks.
• Reviewing and developing SDC constraints.
• Performing timing analysis, debugging timing violations, and driving timing closure with IP Design and SoC PD teams.
• Debugging and resolving CDC/Lint/DFT issues and driving signoff quality.
• Developing scripts and automation flows to improve productivity and methodology.
• Supporting design teams on implementation and signoff-related activities. Preferred Experience
• 5-8 years of experience in Synthesis, Static Timing Analysis, CDC/RDC, Lint, and DFT methodologies.
• Solid hands-on experience with Design Compiler, Fusion Compiler, SpyGlass (Lint/CDC/RDC),



CDC0in, GCA, and related Front-End tools.
• Deep understanding of SDC constraints, setup/hold analysis, path groups, timing exceptions, clocking architecture, and timing closure methodologies.
• Experience reviewing and debugging CDC/RDC violations and driving signoff closure.
• Good understanding of scan/DFT concepts and DFT-related checks.
• Strong knowledge of clock gating, low-power design, and SoC integration methodologies.
• Experience with scripting and automation using TCL, Python, Perl, Shell, and Makefiles.
• Familiarity with RTL design and Verilog is desirable, but not a primary requirement.
• Strong debugging and problem-solving skills.
• Good communication skills and ability to work effectively with geographically distributed teams.

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