• ? Job Title: DFT Engineer (Senior / Manager)
•
• ? Experience Required: 3 to 12 Years
•
• ? Annual CTC Budget: Best in Industry / As per Market Standards
• ?
Location:
Bangalore, India
•
• ⚠️ MANDATORY CRITICAL MATCH CRITERIA (READ FIRST):
• ✅
Experience:
3 to 12 years of dedicated core DFT experience in SoC-level design. A reliable career history (minimum 2 years per organization) is strictly required.
•
• ✅
Education:
B.
E. / B.
Tech / M.
E. / M.
Tech in Electronics, Microelectronics, VLSI, or Electrical Engineering.
•
• ✅ Core
Skills:
Mandatory hands-on experience in ATPG and Gate Level Simulation (GLS), along with experience in Scan Insertion, MBIST, or JTAG/IJTAG/BSCAN.
•
• ✅ Software/Tools: Hands-on debugging and simulation proficiency using Cadence (Xcelium/NCSim), Siemens Tessent, or Synopsys (VCS).
•
• ✅ Communication: Strong communication skills for cross-functional coordination, client interfacing, and internal DFT team mentoring.
•
• ✅ Logistics: Office-based in Bangalore, with flexibility for hybrid/remote setups based on project demands.
•
• ➡️ Position Overview Drive complete SoC-level DFT execution from scan insertion and ATPG to timing simulations and post-silicon debug. You will collaborate with cross-functional STA/PD teams to deliver high-quality fault coverage and robust semiconductor designs.
• ? Core Responsibilities
• ✔️ Execute ATPG pattern generation, fault modeling (Stuck-at, TDF, IDDQ), and test coverage improvement techniques.
• ✔️ Perform zero-delay and SDF timing simulations using Cadence Xcelium, Synopsys VCS, or NCSim in GUI mode.
• ✔️ Integrate SoC-level DFT structures including OCC/OPCG, EDT/Compression logic, MBIST, and JTAG/IJTAG/BSCAN modules.
• ✔️ Define and provide test mode timing constraints to STA and Physical Design (PD) teams. ✔️ Lead post-silicon bring-up and ATE tester debug using shmoo plots and cross-functional team coordination.
How to Apply
? If you meet the requirements outlined in the
job description
and are interested in this opportunity, please email your resume to
[email protected], mentioning your Current CTC, Expected CTC, and Notice Period. #DFT #ATPG #Semiconductor #VLSI #BangaloreJobs
📌 DFT Engineer (Bengaluru)
🏢 Amrapali Services
📍 Bengaluru