Your Role and Responsibilities:

Your Primary Responsibilities Will Include:

- Define and document microarchitecture for assigned functional blocks, including pipeline structure, data-path organisation, and control logic.
- Author clean, synthesisable RTL in VHDL or SystemVerilog, adhering to team coding guidelines and lint/CDC/RDC cleanliness targets.
- Collaborate with architects to evaluate design alternatives and communicate area, power, and frequency trade-offs.
- Drive design debug across simulation, emulation, and post-silicon environments; develop debug strategies and root-cause RTL or logic issues efficiently.
- Own timing closure for assigned blocks: analyse critical paths, apply SDC constraints, guide ECO strategies, and work with physical design to meet frequency targets.
- Review and sign off on verification plans, ensuring functional coverage goals align with the microarchitectural intent.
- Participate in design reviews and contribute to cross-project lessons-learned to improve team-wide processes.
- Mentor junior engineers on RTL quality, debug methodology, and timing fundamentals.

Required Education:

Bachelor's Degree

Preferred Education:

Master's Degree

Required Technical and Qualified Expertise:





- 5-10 years in digital ASIC or processor logic design, Microarchitecture definition and specification authoring.
- RTL coding in SystemVerilog and/or VHDL
- Static timing analysis (STA) and SDC constraint authoring
- Timing closure - path analysis, ECOs, hold/setup fixing
- Design debug: simulation, waveform analysis, emulation
- Logic synthesis (Synopsys DC, Cadence Genus, or equivalent)
- Lint, CDC, and RDC analysis tools (SpyGlass or equivalent)
- Familiarity with formal verification flows
- Cross-functional collaboration with physical design and DFT

Preferred Technical and Professional Experience:

- Experience in high-performance processor, memory subsystem, or high-speed interconnect design (e.g. PCIe, NVLink, OpenCAPI).
- Exposure to power analysis and low-power design techniques (clock gating, power domains, UPF/CPF).
- Post-silicon bring-up and debug experience including lab instrumentation and JTAG-based debug flows.
- Familiarity with emulation platforms (Palladium, Zebu) for pre-silicon debug at speed.
- Track record of driving an RTL block from specification to tapeout on a commercial product.

Years of Experience:5 - 10

📌 Logic Design Engineer (Bengaluru)
🏢 IBM
📍 Bengaluru