Experience & Qualifications:

- BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
- Experience with industry standard ATPG and DFx insertion CAD tools.
- Familiarity with SystemVerilog and UVM.
- Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
- Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
- Good understanding of high-performance, low-power design fundamentals.
- Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
- Exposure to post-silicon testing and tester pattern debug are major assets.
- Experience with Fault Campaigns a plus.
- Strong problem solving and debug skills across various levels of design hierarchies.





Responsibilities:

- Implementation of DFT features into RTL using verilog.
- Understanding of DFT Architectures and micro-architectures.
- ATPG and test coverage analysis using industry standard tools.
- JTAG, Scan Compression, and ASST implementation.
- Gate level simulation using Synopsys VCS and Verdi.
- Support silicon bring-up and debug.
- MBIST planning, implementation, and verification.
- Support Test Engineering on planning, patterns, and debug.
- Develop effective DFx flows and methodology compatible with front end and physical design flows.

📌 Senior Lead Design for Testability (DFT) Engineer (Hyderabad)
🏢 MosChip®
📍 Hyderabad