Role & responsibilities

- Analyze, design, and optimize Machine learning kernels on ML HW accelerator for performance, power, and area efficiency in value tier chipsets.
- Conduct architectural analysis and benchmarking of ML subsystems, identifying bottlenecks and proposing solutions for improved throughput and efficiency.
- Collaborate with hardware and software teams to define and implement enhancements in ML HW microarchitecture, memory hierarchy, and dataflow.
- Develop and validate performance models for AI workloads, including signal processing and ML inference, on embedded platforms.
- Prototype and evaluate new architectural features for ML HW, including quantization, compression, and hardware acceleration techniques.
- Support system-level integration, performance testing, and demo prototyping for commercialization of optimized ML solutions.
- Document architectural analysis, optimization strategies,



and performance results for internal and external stakeholders.

Preferred candidate profile

- Solid background in DSP architecture, embedded NPU design, and low-power AI systems.
- Proven experience in performance analysis, benchmarking, and optimization on any embedded processors (DSP, ARM, RISC-V, NPU).
- Robust programming skills in Embedded C/C++, Python
- Experience with embedded platforms, real-time operating systems, and hardware/software co-design.
- Expertise in both fixed-point and floating-point implementation, with a focus on ML/AI workloads.
- Excellent communication, presentation, and teamwork skills; ability to work independently and across global teams.
- Strong fundamentals of Power modeling and Power analysis

Perks and benefits

📌 Embedded AI Architecture and Systems Engineer (Hyderabad)
🏢 Qualcomm
📍 Hyderabad