MAXVY
- Campus Hiring
- 2027

Location:
Bangalore, Tirunelveli

Experience:
Fresher

Education:
B.
E, M.
E, M.
Tech, B.
Tech Role

Job Description
– Design Verification Engineer Trainee
• Undergo technical training on the essential skills required for VLSI Design Verification.
• Learn the fundamentals of digital electronics and VLSI design concepts.
• Develop basic knowledge of Verilog and SystemVerilog.
• Understand programming fundamentals and logical problem-solving techniques.
• Learn the basics of functional verification and testbench development.
• Gain exposure to simulation tools and waveform analysis.
• Work closely with the Design Verification team under expert guidance.
• Assist in developing and executing test cases and verification scenarios.
• Participate in debugging, issue analysis, and verification activities.
• Complete practical assignments and projects to strengthen technical skills.

Job Description
Website www.maxvytech.com Qualification BE ECE; / MTech VLSI




- 75% throughout education and no history of arrears Job

Location:
Bengaluru/Tirunelveli Salary 4 LPA to start (3 LPA + 1 LPA retention bonus) Service Agreement 4 years Onboarding Process
• Upson selection; online documentation
• 10 days awareness program at Tirunelveli
• 90 working day’s unpaid Academic internship in Tirunelveli
• Joining date after result (will not be confirmed, if any history of arrears found) Offer Letter Will be issued once Academic Internship completed. Interview Process: (to check the basics and fundamentals) for ECE: Aptitude (10); Digital Electronics (15) and Verilog (10) – MCQ Process: Written Test + Technical Discussion + HR Discussion. Job

Location:
Training at Tirunelveli (1 year) must be ready and willing to relocate to Bangalore based on the project needs within 1 year training if needed and work at Bengaluru (3 years)

Salary:
4 LPA

📌 MAXVY - Campus Hiring - 2027 -- Bangalore, Tirunelveli
🏢 MAXVY Technologies
📍 Tirunelveli