Job Role: Senior FPGA Engineer – ASIC Prototyping & Emulation

Location:
Bengaluru, Karnataka, India (On-Site)

Experience:
5+ Years

About the Role
We are seeking a Senior FPGA Prototyping & Emulation Engineer with hands-on expertise in taking pre-silicon ASIC RTL designs and porting/refactoring them for FPGA prototyping platforms. You will own the end-to-end flow from ASIC logic adaptation, clocking/memory refactoring, and Vivado/Quartus synthesis to timing closure and live hardware bring-up.

Key Responsibilities
• ASIC RTL Refactoring & Porting: Convert and adapt synthesizable ASIC RTL (Verilog/SystemVerilog) for FPGA targets. Refactor ASIC-specific logic including gated-clock conversion, reset synchronizers, memory wrapper adaptations, and asynchronous FIFOs.
• Multi-FPGA Partitioning & Prototyping: Build, integrate, and partition top-level SoC/IP environments on FPGA platforms (e.g., Xilinx Virtex UltraScale+, Zynq, Intel Agilex/Stratix, or proFPGA/ZeBu systems).
• Synthesis, STA & Timing Closure: Develop timing constraints (SDC/XDC), perform static timing analysis (STA), and drive timing closure across complex multi-clock designs using Vivado, Quartus Prime Pro, or Libero SoC.
• Live Hardware Bring-Up & Debug: Perform board-level hardware bring-up, protocol analysis, and root-cause debugging using logic analyzers, Vivado ILA, Intel SignalTap,



and protocol analyzers (SerialTek, LeCroy). Mandatory Qualifications &

Requirements:
1. 5+ years of core experience in FPGA Prototyping, Pre-Silicon Emulation, or ASIC RTL Integration. 2. Direct hands-on experience in refactoring ASIC RTL for FPGA implementation (e.g., gated-clock trees, memory macro conversions, and Clock Domain Crossing / CDC resolution using SpyGlass/Questa CDC). 3. Proven experience writing Verilog/SystemVerilog RTL and developing XDC/SDC timing constraints. 4. Deep hands-on experience with high-speed interface protocols: AMBA AXI/AHB/APB, PCIe (Gen3/4/5), CXL, or NoC interconnects. 5. Demonstrated track record of successful FPGA board bring-up, timing closure, and on-chip hardware debugging (Vivado ILA / SignalTap). 6. Solid Linux shell, Tcl scripting, and automated build flow experience. Preferred / Added Advantage:
• Hands-on experience with pre-silicon emulation platforms (Synopsys ZeBu, Siemens proFPGA, or Cadence Palladium/Protium).
• Experience with MicroBlaze/ARM/RISC-V embedded C/ELF validation execution on FPGA platforms. Important Notice:
• This role requires hands-on ASIC RTL porting and refactoring experience. Pure board design, firmware, verification-only (DV), or post-silicon validation profiles will not be considered.

📌 Senior FPGA Engineer – ASIC Prototyping (Bengaluru)
🏢 Rv5 UKSAG
📍 Bengaluru