Job Title: Senior Design Engineer Physical Design

Location: Hyderabad

Duration: 12 Months
510+ years of experience in ASIC/SoC Physical Design from netlist to GDSII.
Expertise in floor planning, power planning, placement, CTS, routing, and physical signoff.
Robust experience in timing closure (setup/hold), MMMC analysis, ECO implementation, and PPA optimization.
Hands-on experience with physical verification (DRC/LVS), SI, IR drop, and EM/Power integrity analysis.
Proficient in EDA tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, and Calibre.
Skilled in Tcl, Python, Perl, and Shell scripting for flow automation and productivity enhancements.
Experience in advanced technology nodes (16nm/7nm/5nm and below) and low-power design methodologies.
Solid collaboration with RTL, STA, DFT, Library, and CAD teams to deliver successful tape-outs.
Proven ability to drive block/full-chip closure and mentor junior engineers.

📌 Physical Design Engineer Hyderabad (India)
🏢 Sunrisesys
📍 India