Designs advanced digital building blocks for various applications, including (but not limited to) power management, low-power & low-voltage applications.

Responsibilities:
• Micro-architecture specification development IP or Sub-System and design documentation
• RTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Timing and power constraints development
• Collaboration with analog design team for mixed-signal designs
• Collaboration with verification team in verification plan development and debug
• Collaboration with physical design team to close the design on timing and power
• Collaboration with firmware design team to close the design system scenarios Minimum Qualification:
• 6 : 10 years' experience in RTL development
• Advanced knowledge of RTL design using VHDL or Verilog/SystemVerilog




• Low power (UPF) implementation. RTL sing-off.
• Experience working closely with Firmware, Verification, DFT & PD team
• Solid communication and presentation skills in English.
• Have expense in Pre-Silicon (FPGA) Validation.
• Engineer must have valuable understanding on conversion of ASIC RTL to FPGA RTL.
• Experience in design partition on FPGA to generate multiple bit file, have good understanding on FPGA clock wizard configuration and building clock tree structure in FPGA.
• Hands-on experience in Vivado tool (Must).
• Experience in FPGA timing closure must. Preferred Qualification:
• Hands-on experience with synthesis.
• Able to work in a team
• Positive problem solving skills and being able to implement solutions autonomously
• Knowledge of mixed signal concepts (added advantage)

📌 Staff Engineer Hyderabad (India)
🏢 Cyient
📍 India