Responsibilities
Verification
Own the verification of complex digital integrated circuits at the block, subsystem, or device level.
Understand the device requirements and functional description to ensure compliance with specifications and error-free operation.
Plan verification activities, develop testbenches, and execute tests.
Develop verification platforms using the UVM methodology and SystemVerilog.
Technical Leadership
Deliver verified designs at the Device, Subsystem or Block level
Partner with a dedicated Design Lead to deliver high-confidence designs
Verify designs implemented in SystemVerilog RTL using industry-standard methodologies.
Domain Expertise
Contribute to the development and enhancement of verification technologies and methodologies.
Cross Functional Responsibility
Collaborate with Software and Validation teams to deliver devices that integrate into a wider system.
Participate in Product Validation during the prototype stage of development.

Requirements/Qualifications




Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering
8+ years of related experience
Excellent analytical and debugging skills and the ability to proactively solve issues
Proven ability to thrive on, learn and adapt to current methodologies and technologies
Solid coding skills
Experience using one or more of SystemVerilog/Verilog/VHDL, Tcl/Perl/Python, C/C++
Excellent verbal and written communication skills in English
Experience with verification methodologies, including UVM, formal verification, and constrained-random verification.

Travel Time

0% - 25%

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📌 Principal Verification Engineer Bengaluru (India)
🏢 Microchip Technology
📍 India