24 Oct
|
BITSILICA
|
Bengaluru
24 Oct
BITSILICA
Bengaluru
• 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and SoC level.
• Experience in ATPG pattern generation, coverage analysis
• Experience with timing and no-timing simulations
• Experience in Memory-BIST
• Have understanding of SSN architecture, clock architecture, OCC
Location:
Bangalore
📌 Senior Staff Engineer (Bengaluru)
🏢 BITSILICA
📍 Bengaluru