Static Timing Analysis: Lead (Chip Level) (Bengaluru)

Static Timing Analysis: Lead (Chip Level) (Bengaluru)

24 Oct
|
Lakshya Software Technologies
|
Bengaluru

24 Oct

Lakshya Software Technologies

Bengaluru

Static Timing Analysis: Lead (Chip Level)

Experience: 10-15 yrs | Positions: 2

Responsibilities

∙Own chip-level STA, including constraint writing, quality checks, and budgeting analysis

∙Drive top-level timing closure and sign-off

∙Lead the STA team and coordinate with PD and design teams

Skills

∙Expert in PrimeTime/Tempus, SDC, and exceptions (CDC, false/multicycle paths)

∙OCV/AOCV/POCV, SI, and MCMM analysis at advanced nodes

📌 Static Timing Analysis: Lead (Chip Level) (Bengaluru)
🏢 Lakshya Software Technologies
📍 Bengaluru

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