Looking for an experienced ASIC/SoC DV Engineer with hands-on Cadence Palladium experience to develop and debug emulation environments for pre-silicon verification and SoC software validation.
Key Skills:
- Minimum 3+ years of Emulation experience
- Hands-on experience with Cadence Palladium / Zebu
- Solid Simulation & Emulation experience
- Hardware Transactor development and debugging
- Basic SystemVerilog / UVM knowledge
- Familiarity with bus protocols