JD for your reference:

Position: Design Verification Engineer

Location: Bangalore

Experience: 6+ years

Priority: Immediate

Requirements:

Digital / SoC Verification with 6+ years of relevant experience

Strong expertise in SystemVerilog (SV) and UVM

Hands-on experience with PCIe and/or UCIe protocols

Strong understanding of SoC architecture and verification methodologies

Good programming skills in C / C++

Test Case Development – ability to develop comprehensive and reusable verification test cases

Test Plan Development – experience in defining verification strategies, test plans, coverage goals, and execution

Robust debugging and failure-analysis skills

Experience in identifying, reproducing, analyzing, and resolving complex verification issues

Good understanding of functional verification, coverage, regression, and verification closure

📌 Senior Design Verification Engineer (Bengaluru)
🏢 Modernize Chip Solutions
📍 Bengaluru