24 Oct
|
Cyient
|
Hyderabad
We are seeking a highly skilled Senior Analog Layout Engineer with solid experience in advanced FinFET technology nodes (7nm and below) and high-speed analog/mixed-signal layout design. The ideal candidate will be responsible for translating schematics into high-quality physical layouts while ensuring compliance with foundry design rules, performance requirements, and project specifications.
The engineer will work closely with circuit designers and verification teams to develop robust layouts for high-speed analog and mixed-signal IPs, ensuring successful DRC/LVS closure and post-layout verification.
📌 Senior Analog Layout Engineer (Hyderabad)
🏢 Cyient
📍 Hyderabad