: Physical Design / STA & Synthesis Engineer

Experience: 4+ Years

Location: Bangalore / Hyderabad / Chennai

Notice Period: Immediate to 30 Days Preferred

Job Overview

We are looking for experienced VLSI Engineers with expertise in Physical Design, Static Timing Analysis (STA), and Synthesis. Candidates should have hands-on experience with Cadence Innovus and a strong understanding of RTL-to-GDSII implementation flow.

Key Responsibilities

- Perform RTL-to-GDSII implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.
- Execute synthesis, timing analysis, and design optimization to meet PPA targets.
- Perform Static Timing Analysis (STA), including setup and hold analysis, timing closure, and timing violation debugging.
- Work on timing optimization, congestion analysis, and power, performance, and area (PPA) improvements.
- Handle timing constraints, including SDC creation and validation.




- Analyze and resolve timing issues across different PVT corners and modes.
- Collaborate with RTL, synthesis, physical design, and signoff teams to ensure successful design closure.

Required Technical Skills
- 4+ years of experience in VLSI Physical Design, STA, and/or Synthesis.
- Hands-on experience with Cadence Innovus for physical implementation.
- Solid understanding of RTL synthesis and the RTL-to-GDSII flow.
- Experience with Static Timing Analysis, setup/hold checks, and timing closure.
- Knowledge of floorplanning, placement, CTS, routing, and physical design optimization.
- Experience with timing constraints, SDC, and timing reports.
- Familiarity with industry-standard EDA tools and scripting using Tcl or Python.

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