Greetings from Artech

We are hiring for ASIC/FPGA Verification Engineer / Design Verification Engineer || Artech_Aerospace || Bangalore || Hybrid

Experience : 6+ Years

Location : Bangalore

Notice Period : Immediate to 15 Days

Mode of work : Hybrid

[email protected]

Skills : #DVEngineer #ASIC #FPGA #PCIeGen5 #Make #Perl #Python #DO -254

Preferred Qualifications (Desired Skills/Experience):

1. Experience in Ip, Subsystem and system along with Verification components developed for one ASIC/FPGA Product.
2. Experience identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements.
3. Expert in using object-oriented programing in System Verilog along with UVM methodology.
4. Expert in using Universal Verification Methodology (UVM):
5. Experience crafting drivers, monitors, predictors,



coverage model and scoreboards and UVCs.Work experience crafting a self-checking scoreboard and Reference models from scratch for SoCs/ASIC/FPGA.Experience in crafting SVA -Assertions for agile simulation and formal verification Experience in coverage (code and functional) signoff, by reviewing complex ASIC and FPGA RTL code.
6. Work experience using Linux or Unix terminal commands.Experience using scripting languages: Make, Perl, Python, shell scripts, etc.
7. Experience using Revision Control Systems: Subversion (SVN), CVS, Git.
8. Experience in Power aware simulation debug along Gate level simulation debugExperience in Avionics protocols is a plus.
9. Experience in DO -254 for ASIC /FPGA is a plus

Typical Education amp; Experience: Bachelor, Master degree In Electronics Engineering , Electrical Engineering with 6 to 8 years of experience amp; Masters degree with 6+ years of experience.

📌 Design Verification Engineer (Bangalore Metropolitan Area)
🏢 Artech
📍 Bangalore Metropolitan Area