Key Responsibilities

- Perform pre-silicon FPGA prototyping and bring-up of the ASA IP digital subsystem.
- Partition Camera Serializer digital logic for Xilinx VCU128 and Alveo FPGA platforms.
- Implement FPGA-friendly clock domain replacements for PHY-derived clocks.
- Execute ASA IP FPGA bring-up, including SoC slave bus access, ASEP stream validation, and OAM link establishment using reference hardware.
- Perform CSI-2 video capture and pixel integrity validation using an FPGA-based MIPI sink.
- Develop automation and bring-up scripts using Python and Tcl.
- Debug FPGA hardware using ILA, VIO, and ChipScope tools.
- Conduct lab validation using oscilloscopes and BERTscope.
- Collaborate with RTL, hardware, and validation teams to troubleshoot integration and bring-up issues.

Required Skills And Qualifications

- 5+ years of relevant experience in FPGA prototyping, hardware bring-up,



and debugging.
- Hands-on experience with Xilinx FPGA platforms, particularly VCU128 and/or Alveo.
- Proficiency in Xilinx Vivado and Vitis tools.
- Good understanding of SystemVerilog RTL and digital logic design.
- Solid Tcl scripting skills; experience with Python automation.
- Experience with FPGA-based subsystem integration, validation, and hardware debugging.

Preferred Skills

- Experience with SerDes or MIPI interface bring-up.
- Knowledge of CSI-2 video interfaces and pixel integrity validation.
- Experience with high-speed serial links, clock domain management, and FPGA-based prototyping.
- Familiarity with lab instruments such as oscilloscopes and BERTscope.

📌 FPGA Prototyping Engineer (Bengaluru)
🏢 Synectics Apac
📍 Bengaluru