Provides services in transforming the RTL design into a physical layout of the chip using Synopsys
Fusion Compiler synthesis and place-and-route tools. The physical design process involves specifying various constraints on the netlist, such as timing, power, area and design rules, and optimizing the layout for performance, quality, and reliability. We work on physical verification techniques such as
Siemens Caliber DRC, LVS, antenna and density, especially in the latest nodes such as 5nm and 3nm.
RTL to GDSII
Synthesis, Placement and Routing using Fusion Compiler
Block and SOC Floor planning using Fusion Compiler