This role is for one of Weekday's clients Min Experience: 8+ years

Location: Bengaluru, Noida

JobType: full time

Own DFT for a full SoC. Derive the DFT architecture with the customer and product engineering teams, lead a team of 4-6 engineers, drive DFT sign-off, and support silicon bring-up.

Experience: 8 to 9 years. Must have 5 or more tapeouts, with at least 1 as DFT lead.

Requirements Desired Skills:

- Defines SoC DFT architecture against test time, test cost, coverage, test power and pin budget
- Exposure to streaming scan networks (SSN) or tile-based hierarchical DFT for large SoCs
- Applies advanced fault models: cell-aware, path delay, small delay defect and IDDQ
- Owns SoC-wide MBIST and repair architecture, including shared-bus memory test
- Low-power DFT:



power-domain aware scan and test-mode power management (UPF-aware DFT)
- Owns DFT-mode STA sign-off criteria with the STA team
- Leads post-silicon work: ATE bring-up, failing-pattern diagnosis and yield diagnosis support
- Owns schedule, effort estimates, risk tracking and weekly status to the customer
- Leads DFT plan and sign-off reviews, and interviews candidates
- LBIST and in-system test for automotive (ISO 26262) is a plus

Must-have Skills DFT, SoC, tapeout Good-to-have Skills DFT architecture, streaming scan networks, tile-based hierarchical DFT

📌 Technical Lead - DFT (Bengaluru)
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