Experience: 9+ Years

Employment Type: Full time

Location: Bangalore/ Hyderabad

Client/Company: Top-Tier Semiconductor Client

Position Summary

We are seeking a highly skilled and experienced Lead Physical Design Engineer to own and drive full-chip and block-level ASIC/SoC physical implementation. In this role, you will lead advanced node (7nm/5nm/4nm/3nm and below) physical design efforts, working directly with top-tier semiconductor technology. You will collaborate closely with RTL, Synthesis, DFT, Timing, and Foundry teams to deliver high-performance, power-efficient, and tapeout-ready silicon.

Key Responsibilities

- Full-Flow P&R;: Lead block and top-level implementation (floorplan, CTS, routing) on advanced nodes (5nm/3nm).
- Design Closure: Drive timing (STA), power/IR-drop, and physical verification (DRC/LVS) to guarantee zero-defect tapeout.
- Technical Leadership: Mentor physical design engineers, enforce execution standards, and drive project milestones.
- Cross-Team Alignment: Partner with RTL, Synthesis, DFT, and Foundry teams to resolve design bottlenecks.

Required Qualifications & Experience

- Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication Engineering, Microelectronics, or a related discipline.
- Experience:



9+ years of hands-on physical design experience with multiple successful tapeouts in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
- Tool Expertise: Proficient in industry-standard EDA physical design toolsuites:
- P&R;: Synopsys Fusion Compiler / ICC2 or Cadence Innovus.
- STA: Synopsys Tempus or PrimeTime.
- Physical Verification: Siemens Calibre or Synopsys IC Validator.
- Technical Mastery: Deep understanding of floorplanning, power routing, CTS architectures, IR drop/EM analysis (Voltus/RedHawk), and timing closure methodologies.
- Leadership Skills: Proven track record of leading complex sub-systems or full-chip implementations, managing project timelines, and mentoring junior/mid-level engineers.

Preferred Qualifications

- Prior experience with high-speed interfaces (PCIe, DDR, Ethernet, SerDes) or complex SoC architectures.
- Hands-on scripting capability in TCL, Python, or Perl to build/enhance automated design flows.
- Exposure to post-silicon bring-up and physical debug support.

What We Offer

- Full-time employment with a global leader in semiconductor innovation.
- Competitive compensation package, performance bonuses, and comprehensive benefits.
- Opportunity to work on cutting-edge next-gen SoC products and advanced packaging technologies.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 SKaaS- Skills as a Service
📍 Bengaluru