This role is for one of Weekday's clients Min Experience: 12+ years

Location: Bengaluru

JobType: full-time

Act as the senior DFT technical authority across the organization. Define DFT architecture and methodology for the most complex SoCs and multi-die designs, solve the hardest silicon test escalations, and support pre-sales with technical solutioning. Influence comes through principals and leads rather than direct reports.

Experience: 12 to 14 years. Must have 8 or more tapeouts, including complex SoCs, and a record of defining DFT methodology at organization level.

Requirements Desired Skills:

- Defines DFT for chiplet and 2.5D/3D designs: IEEE 1838, die-to-die interface test, known-valuable-die strategy and UCIe test. 2. Expert in advanced techniques: streaming scan, cell-aware test, in-system test and silicon lifecycle management
- Owns organization-level DFT standards: architecture templates, flows,



sign-off criteria and review checklists
- Evaluates and selects DFT tools and ATE flows, and builds strong relationships with EDA vendors
- Is the escalation point for silicon test failures, yield issues and test-cost problems across programs
- Provides technical solutioning for pre-sales: DFT approach, effort models and risk assessment for customer proposals
- Mentors principals and DFT leads, and builds DFT depth across the practice. Represents the company in technical discussions with customer architects and test engineering teams
- Patents, papers or talks (ITC, VTS, DAC) are a plus

Must-have Skills DFT Architect, Chiplet DFT, 3D-IC Test Good-to-have Skills multi-die or chiplet programs, EDA tool evaluation, pre-sales solutioning

📌 Senior Engineering Lead - DFT (Bengaluru)
🏢 Weekday AI (YC W21)
📍 Bengaluru