26 Oct
|
Lakshya Software Technologies
|
Bengaluru
26 Oct
Lakshya Software Technologies
Bengaluru
Physical Design: Chip Level Lead Experience: 10-15 yrs | Positions: 2
Responsibilities
- Own chip/SS-level floorplanning, partitioning, and integration
- Define block-level budgets and constraints, and drive top-level timing closure
- Lead PD teams and coordinate with RTL, DFT, STA, and PV teams
- Drive power, area, and congestion optimization at chip level
Skills
- Hands-on chip-level PnR, hierarchical flows, clock and power planning
- Solid knowledge of IO/bump planning, feedthroughs, and top-level closure
- Experience taping out multiple chips at advanced nodes
📌 Design and Planning Lead (Bengaluru)
🏢 Lakshya Software Technologies
📍 Bengaluru