Own physical implementation solutioning, methodology definition, PPA strategy, and implementation planning for complex SoCs. Serve as technical authority for physical design architecture and feasibility.
- Define implementation methodologies for large chips.
- Develop floorplanning and partitioning strategies for SoC Level.
- Drive PPA closure approach from Spec to GDS-II.
- Conduct early feasibility and QoR assessments.
- Define clocking, power, and congestion strategies.
- Guide implementation teams globally.
- TSMC Tech Node experience is must
- Experience on AI based EDA tools is required e.g. DSO or Cerberus etc.
- Review signoff readiness and implementation risks.
- Support customer technical engagements and project estimation.
Your Profile
- 12+ years in Physical Design.
- Multiple tape-outs in advanced nodes (10nm and below).
- Expertise in floorplanning, CTS, timing closure, and power optimization.
- Strong knowledge of Synopsys ICC2/Fusion Compiler and/or Cadence Innovus.
- Experience with UPF and multi-voltage designs.
- Experience with large SoCs (>100M gates).
- Strong understanding of signoff methodologies.
- Should be able to support and delivery multiple projects simultaneously.
- HBM/HMC memory systems
- We value flexibility and support our employees with hybrid work options and adaptable schedules to maintain a healthy work-life balance.
- Our inclusive culture brings together diverse professionals committed to growth, innovation, and excellence.
- At Capgemini, you can work on cutting-edge projects in technology and engineering with industry leaders and contribute to creative semiconductor solutions.