? We’re Hiring | Design Verification Engineer ? Hyderabad | ?

Experience:
3–8 Years ⏳ Notice Period: 15–30 Days Vaaluka Solutions is hiring Design Verification Engineers with robust expertise in AXI and high-speed protocols, with experience in SoC/IP/Subsystem verification. ? Must-Have Skills
• Strong expertise in AXI
• Experience with one or more: PCIe, USB, DDR, Ethernet, CXL, UCIe
• Strong hands-on experience in System Verilog & UVM
• Experience in C-based test/test bench development
• Experience in SoC/IP/Subsystem-level verification
• Strong debugging & coverage closure skills
• Knowledge of Python or Perl scripting
• Experience in test-plan development ? Role Highlights




• Develop verification test plans and test cases
• Work with UVM-SV and C-based flows
• Debug SoC/IP/Subsystem-level failures
• Develop assertions & functional coverage
• Drive code and functional coverage closure
• Mentor junior engineers and collaborate with global teams ? Interested candidates, please share your updated resume at: [email protected] #Hiring #VLSIJobs #DesignVerification #SoCVerification #IPVerification #SubsystemVerification #UVM #SystemVerilog #AXI #PCIe #DDR #Ethernet #CXL #UCIe #HyderabadJobs

📌 Senior Design Verification Engineer (Hyderabad)
🏢 Vaaluka Solutions
📍 Hyderabad