Job Title: Design Verification Faculty / Trainer – VLSI Company: MOSart Labs Pvt Ltd

Location:
Hyderabad — In office CTC: Up to ₹12 LPA, based on experience and expertise

About the Role
MOSart Labs is seeking an experienced Design Verification Faculty / Trainer to teach and mentor students in our VLSI training programs. The candidate should have strong technical knowledge, hands-on verification experience, and prior experience delivering structured technical training. This is a dedicated faculty and training role, focused on classroom delivery, practical labs, student projects, and interview preparation.

Key Responsibilities
• Conduct instructor-led classes and practical sessions covering digital fundamentals, Verilog, SystemVerilog, and UVM.
• Teach verification planning, testbench architecture, constrained-random verification, assertions, functional coverage, and coverage closure.
• Train students to develop reusable UVM components, including agents, drivers, monitors, sequencers, scoreboards, and environments.
• Explain RTL simulation, waveform analysis, debugging techniques, and verification best practices.
• Guide students through practical verification projects involving interfaces and protocols such as APB, AHB, and AXI.
• Prepare lesson plans, lab exercises, assignments, assessments, and project documentation.




• Evaluate student progress, resolve technical doubts, and provide individual mentoring.
• Conduct mock interviews and help students explain their projects and verification approach confidently.
• Update training materials to reflect relevant industry practices. Required Qualifications and Skills
• M.
Tech in ECE, EEE, VLSI, Microelectronics, or a related discipline.
• PHD in Design Verification is Mandatory.
• Prior experience teaching or training students in VLSI Design Verification is required.
• Strong knowledge of digital electronics, Verilog, SystemVerilog, and UVM.
• Hands-on experience developing testbenches and UVM verification environments.
• Sound understanding of SystemVerilog Assertions (SVA), functional coverage, code coverage, and debugging.
• Practical experience with at least one major simulator: Siemens Questa, Synopsys VCS, or Cadence Xcelium.
• Familiarity with Linux and scripting for simulation workflows.
• Excellent communication, classroom delivery, and student mentoring skills.
• Ability to explain complex concepts clearly and deliver practical, project-based training. #Hiring #DesignVerification #VLSITrainer #SystemVerilog #UVM #FacultyHiring #HyderabadJobs #MOSartLabs

📌 Design Verification (Hyderabad)
🏢 MOSart Labs
📍 Hyderabad