Role Title: Lead Physical Design Engineer

Location: Bangalore

Employment Type: Full-time

Experience Level: 8years to 20 Years

Seniority Level: Senior Lead/Director

Role Overview

We are seeking an experienced and technically driven Lead / Principal Physical Design Engineer with comprehensive hands-on ownership of full-chip hierarchical implementations. In this role, you will lead complex SoC designs from Netlist/RTL handoff through GDSII tape-out on advanced FinFET/GAA process nodes (e.g., 7nm, 5nm, 3nm, or below).

You will work closely with Architecture, RTL, DFT, CAD, and Foundry Interface teams to drive timing closure (STA), signal integrity, power integrity (IR/EM), physical verification, and chip assembly. For candidates at the senior end of this bracket (15–20 years), the role includes defining chip floorplanning strategy, technical mentorship, and driving cross-functional execution.

Key Responsibilities

- Full-Chip Hierarchy & Floorplanning:
- Define and drive full-chip top-level floorplanning, power grid architecture (PG mesh), pad placement, macro placement, bump planning, and pin assignments.
- Plan partition boundaries, pin interfaces, and budgeting for multi-million/billion-gate hierarchical SoC designs.
- Place & Route (P&R;) Execution:
- Own end-to-end P&R; implementation (Floorplanning, Placement, CTS/Multi-Source CTS, Routing, Post-Route Optimization).
- Drive low-power implementation strategies using UPF/CPF (multi-voltage domains, power gating, retention logic, level shifters).
- Clock Tree Synthesis (CTS) & Timing Closure (STA):
- Architect low-skew, low-power, balanced clock trees across complex asynchronous clock domains and multi-corner multi-mode (MCMM) scenarios.
- Perform full-chip static timing analysis, signal integrity (SI) cross-talk analysis, ECO generation (functional and timing), and constraint validation.
- Power Integrity & Reliability:
- Execute and sign off static and dynamic IR drop, Electromigration (EM), and power rail analysis (RedHawk/Voltus).
- Drive package-die co-design, ESD protection networks, and decoupling capacitor optimization.




- Physical Verification & Sign-off:
- Lead DRC, LVS, ERC, Antenna, and XOR sign-off at the top level.
- Coordinate with foundry teams to interpret design rule manuals (DRMs), resolve complex design-rule violations, and manage waiver reviews.
- Methodology, Automation & Leadership (8–20 yrs focus):
- Develop, enhance, and maintain production-grade design flows using Tcl, Python, and shell scripts.
- Interface with CAD/EDA vendors to deploy advanced tool capabilities and address tool anomalies.
- Mentor junior and mid-level engineers, conduct design reviews, and establish milestone execution schedules for successful tape-outs.

Required Technical Skills & Qualifications
- Education: B.Tech / B.E / M.Tech / M.S. in Electrical Engineering, Electronics & Communication, VLSI Design, or a closely related field.
- Experience: 8 to 20 years of dedicated experience in ASIC/SoC physical design with a track record of multiple taped-out chips.
- Process Nodes: Direct, proven experience in advanced FinFET/GAA nodes (16nm/12nm, 7nm, 5nm, 3nm).
- EDA Tool Proficiency:
- P&R;: Synopsys ICC2 / Fusion Compiler OR Cadence Innovus.
- STA: Synopsys PrimeTime / PrimeTime-SI OR Cadence Tempus.
- Physical Verification: Siemens EDA Calibre (DRC/LVS/PERC) OR Synopsys IC Validator.
- IR/EM Sign-off: Ansys RedHawk-SC / Apache OR Cadence Voltus.
- Scripting: Advanced proficiency in Tcl and Python; standard Unix/Linux shell scripting.
- Design Domains: Deep understanding of high-speed interfaces (PCIe, DDR/LPDDR, HBM, Ethernet, SerDes) and their integration constraints.

Desirable / Preferred Qualifications
- Direct experience managing 3D-IC / 2.5D packaging, CoWoS, or chiplet-based physical integration.




- Experience handling hierarchical chip assembly for designs exceeding 500M–1B+ gates.
- Familiarity with machine learning-assisted P&R; optimization features within modern EDA suites (e.g., DSO.ai, Cerebrus).
- Strong background in top-level constraint generation, budget apportionment, and SDC validation.

About ACL Digital | An ALTEN Group company

Website: www.acldigital.com | www.alten.com

Headquarters: Santa Clara, California

Founded: 1992

· ACL Digital - ALTEN is 3rd Largest Engineering services company in the world

· We are now “Outstanding Place to work certified”

· Acquired Si2chip Technologies ,Wafer Space Semiconductor & Coqube semiconductor

· 47,200+ Employees from 75 nationalities

ACL Digital is a design-led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy, to design, implementation, and management we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enable large Enterprises, SMBs and start-ups to transform.

A pioneer in delivering Business Innovation, Integration and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges. With a multi-cultural and transnational talent and as part of the ALTEN Group comprising over 50000+ employees spread across more than 30 countries, it promotes a collaborative knowledge-building environment.

Specialties

Digital Experience, Product Innovation, Technology IT Consulting, Business Consulting Solutions, IT Service Provider, Business Analytics, Operations Consulting, Digital Transformation Consulting, SAP Oracle Netsuite, Networking and Telecom, Embedded and Semiconductor, Life Sciences, Healthcare, Product Innovation & Engineering, Professional Services, and Enterprise Application

).

Interested can share Cv to [email protected] along with the details:

Years of experience

Relevant years of Experience

Current CTC

Expected CTC

Any offers in hand

Notice period

📌 Lead / Principal Physical Design Engineer – Full-Chip / SoC (Bengaluru)
🏢 ACL Digital
📍 Bengaluru