Role Overview

We are seeking a highly motivated Lead Physical Design Engineer to drive the physical implementation of next-generation, high-performance SoCs. The role involves leading physical design activities from RTL-to-GDSII, mentoring engineers, and ensuring successful tape-outs with optimal power, performance, and area (PPA).

Key Responsibilities

- Lead and mentor a team of Physical Design engineers.
- Drive end-to-end implementation including Floorplanning, Power Planning, Placement, CTS, Routing, and PPA optimization.
- Perform timing closure across MMMC scenarios using STA methodologies.
- Execute and analyze EM/IR, power intent (UPF/CPF), and reliability checks.
- Achieve sign-off quality for DRC, LVS, ERC, and Antenna verification.
- Collaborate with RTL, DFT, Verification, and Architecture teams to resolve design challenges.
- Develop and enhance automation flows using TCL, Python, and Perl.

Requirements





Required Qualifications

- Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.
- 6-9 years of hands-on experience in Physical Design.
- Strong expertise in ASIC implementation and advanced node design (7nm/5nm/3nm preferred).

- Experience with
- ICC2 / Fusion Compiler or Cadence Innovus

- PrimeTime or Tempus
- Calibre / ICV / Pegasus

- RedHawk or Voltus

- Proficiency in TCL, Python, Perl, and Make.
- Robust problem-solving, debugging, and stakeholder management skills.

Preferred Qualifications

- Experience with CPU/GPU or high-performance SoC designs.
- Exposure to advanced packaging technologies such as 2.5D, 3D-IC, and Chiplets.
- Familiarity with AI/ML-driven EDA optimization methodologies.

📌 Lead Physical Design Engineer (Bengaluru)
🏢 SIGNOFF SEMICONDUCTORS
📍 Bengaluru