Experience:
8+ Years SOC/IP. Looking for an Senior/Lead ASIC Verification Engineer experience in verification of IP/SOC.
• Must have experience in System Verilog, UVM, C.
• Ethernet/PCIe/Chi protocol knowledge
• Should have positive debugging and analytical skills.
• Good to have Scripting knowledge (Python/Perl/shell).
• Good communication skills
• Hands-on experience in Front-end verification tools.
• Desirable to have knowledge of Power aware verification, GLS, Formal Verification. Roles And Responsibilities
• Able to Lead and motivate the team within the constraints of tight schedules.
• Responsible for verifying the ASIC design, architecture and microarchitecture using advanced verification methodologies.
• You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Come up with test plans, tests.

📌 DV Lead (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru