Company Description SignOff Semiconductors Pvt. Ltd. is a leading VLSI design services company headquartered in Bangalore, India, providing high-quality semiconductor design solutions to global fabless companies, IDMs, ASIC developers, and SoC innovators. Founded in 2015 by experienced professionals from Intel and AMD, the company is built on strong values of quality, commitment, and predictable first-pass silicon success. SignOff offers end-to-end ASIC and SoC design services, from specification to GDSII, through flexible engagement models such as Offshore Development Centers, dedicated engineering teams, turnkey execution, and staff augmentation. Its core expertise spans RTL design, functional verification, DFT, physical design, STA, low-power design, analog and mixed-signal, IP integration, and full-chip implementation across advanced nodes including 2nm, 3nm, 5nm, 7nm, and beyond. With a culture of engineering excellence and customer-centric delivery, SignOff supports next-generation AI, networking, automotive, HPC, data center, wireless, and custom ASIC programs for leading semiconductor companies worldwide. Role Description The Physical Design Manager is responsible for leading and executing RTL-to-GDSII implementation for complex ASIC and SoC projects, ensuring robust physical design, timing closure, power optimization, and signoff quality. This is a full time, on-site role based in Bengaluru, where the manager will oversee floorplanning, placement, clock tree synthesis, routing,



and physical verification activities across multiple technology nodes. The role involves managing and mentoring physical design engineers, defining implementation methodologies and best practices, and coordinating with RTL, verification, DFT, STA, and analog teams to resolve design and integration issues. The Physical Design Manager will review constraints, analyze congestion and IR-drop, drive ECO strategies, and ensure that schedules, quality metrics, and tape-out milestones are consistently met. The role also includes technical collaboration with EDA vendors and foundry partners, supporting customer interactions, and contributing to continuous improvement of flows and automation. Qualifications
• Strong expertise in physical design implementation (floorplanning, placement, CTS, routing, optimization) and signoff across advanced technology nodes.
• Hands-on experience with STA, timing closure, signal integrity, clock-domain management, and constraint development using industry-standard EDA tools.
• Knowledge of low-power design techniques, power optimization, IR-drop analysis, EM checks, and power intent (UPF/CPF) implementation.
• Experience with physical verification flows including DRC, LVS, antenna checks, and reliability signoff in collaboration with foundry/PDK teams.
• Proven ability to lead and mentor engineering teams, manage project plans, and coordinate cross-functional activities with RTL, verification, and DFT groups.

📌 Physical Design Manager (Bengaluru)
🏢 SignOff Semiconductors
📍 Bengaluru