Memory Layout Design Engineer

Location:
Bengaluru, India

Experience:
6–12 Years Role Overview We are seeking a highly skilled Memory Layout Design Engineer with deep expertise in full-custom SRAM and memory layout development at advanced technology nodes (2nm, 3nm, 5nm). The ideal candidate will drive memory layout architecture, physical implementation, PPA optimization, and sign-off for high-performance, high-density memory IPs used in complex SoC designs.

Key Responsibilities
• Lead full-custom layout development of SRAM bitcells, memory arrays, register files, and memory peripheral circuits.
• Own layout implementation for sense amplifiers, write drivers, row/column decoders, precharge circuits, and read/write assist circuits.
• Drive layout optimization for Power, Performance, and Area (PPA) across advanced technology nodes.
• Implement complex layouts targeting 2nm/3nm nanosheet or GAA and 5nm FinFET technologies, accounting for foundry-specific process requirements.
• Optimize transistor placement, device matching, routing topology, parasitic capacitance, and critical signal paths.
• Drive memory macro floorplanning, array integration, power distribution, and hierarchical layout assembly.
• Perform and debug DRC, LVS, ERC, antenna, and reliability checks to achieve physical verification closure.
• Support parasitic extraction (PEX), post-layout simulation, and circuit-to-layout correlation.
• Resolve advanced-node challenges involving restrictive design rules, multi-patterning, electromigration, IR drop, and layout-dependent effects.
• Collaborate with circuit design, memory compiler, CAD, and process technology teams to deliver silicon-ready memory IP.
• Own layout quality, technical reviews, design milestones, and tape-out readiness. Required Technical Qualifications
• 6–12 years of hands-on experience in full-custom memory layout design, with demonstrated ownership of complex memory blocks.




• Robust expertise in SRAM bitcell, memory array, register-file, and peripheral circuit layouts.
• Practical experience with advanced technology nodes, preferably 5nm, 3nm, or 2nm, including FinFET or GAA/nanosheet process constraints.
• Deep understanding of transistor-level layout, device matching, symmetry, layout-dependent effects (LDE), and parasitic-aware optimization.
• Strong knowledge of advanced-node DRC/LVS, density rules, routing constraints, and physical verification methodologies.
• Hands-on experience with Cadence Virtuoso Layout Suite and physical verification tools such as Siemens Calibre or equivalent.
• Experience with PEX, EM/IR analysis, and layout optimization for timing, power, and area.
• Strong understanding of SRAM architecture, memory compiler structures, and high-density layout methodologies.
• Experience independently driving layout blocks from schematic handoff through sign-off and tape-out. Preferred Qualifications
• Experience with TSMC N5/N3/N2 or equivalent advanced foundry processes.
• Exposure to SRAM compiler development, multi-bank memories, and high-performance register-file macros.
• Knowledge of GAA/nanosheet device architecture, restrictive design rules, and advanced-node routing methodologies.
• Experience with high-volume silicon products and post-silicon layout-related debug.
• Ability to mentor engineers, conduct layout reviews, and drive cross-functional technical decisions.
• B.
E./B.
Tech or M.
E./M.
Tech in Electronics, Electrical Engineering, Microelectronics, or related disciplines. What Sets You Apart
• Proven ownership of complex SRAM or memory macro layout development at advanced nodes.
• Strong ability to solve challenging layout problems involving area, parasitics, manufacturability, and reliability.
• Deep technical understanding of FinFET/GAA layout constraints and memory circuit implementation.
• Ability to deliver production-quality memory IP with minimal supervision.

📌 Memory Layout Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru