• Around 5-8 years of minimum exp in Synthesis/Constraints Development and Validation/Timing Closure and Sign-off ( blocks/fullchip)
• Complete Ownership of Subsystem level STA closure, Includes giving feedback to PnR owner
• Hands on experience with PrimeTime is must.
• Good debugging experience on Timing issues and debug the same independently
• Understanding of timing constraints and constraints related debugging skills
• Should have worked on lower tech nodes like 7nm , 5nm and below.
• Understanding of scripting language like tcl, perl etc is added.
• Should be positive Team player.
📌 Sr Engineer STA (Bengaluru)
🏢 UST
📍 Bengaluru