Senior Design Verification Engineer (Hyderabad)

Senior Design Verification Engineer (Hyderabad)

27 Oct
|
Recruito
|
Hyderabad

27 Oct

Recruito

Hyderabad

Responsibilities

- Develop test plans and verification strategies for IP and SoC designs.
- Build and maintain UVM-based testbenches.
- Develop directed and random test cases to verify functionality and corner cases.
- Debug simulation failures and resolve design issues with engineering teams.
- Verify protocols such as DDR, PCIe, or Ethernet.
- Achieve code and functional coverage closure.
- Collaborate with RTL, design, validation, and software teams.
- Automate testing and regression using Python, Perl, or shell scripting.

Requirements

- Hands-on design verification experience.
- Expertise in at least one protocol: DDR, PCIe, or Ethernet.
- Proficiency in Verilog, SystemVerilog, and UVM.
- Robust digital design and verification fundamentals.
- Experience with industry-standard simulators and debugging.

📌 Senior Design Verification Engineer (Hyderabad)
🏢 Recruito
📍 Hyderabad

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