RTL - FPGA Design Engineer
Experience : 2-4 years
Location : Hyderabad
Take ownership of end-to-end Xilinx Vivado flows, including synthesis, implementation, XDC constraints, DRC, and bitstream generation.
Drive regression builds and automation scripting while collaborating with firmware and board teams for hardware bring-up and validation.
Bring robust hands-on expertise in AXI protocols, embedded I/O interfaces, register mapping, and comprehensive design documentation.
Interested candidates can share their updated resume directly with
[email protected].
📌 RTL - FPGA Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad