Role & responsibilities
Develop and implement DFT architectures for ASIC/SoC designs.
Perform scan insertion and scan-chain implementation.
Generate and analyze ATPG patterns for stuck-at and transition faults.
Perform DFT Design Rule Checks (DRC) and resolve violations.
Work on Memory Built-In Self-Test (MBIST) and JTAG implementation.
Analyze fault coverage and optimize test patterns.
Debug DFT-related issues and collaborate with RTL, Physical Design, and Verification teams.
Support post-DFT verification and manufacturing test requirements.
Prepare technical documentation and reports.