Solid proficiency in Verilog/SystemVerilog RTL coding.
Positive understanding of digital design fundamentals, FSMs, pipelining, clock-domain crossing, and timing concepts.
Experience in ASIC/FPGA design and development flows.
Knowledge of synthesis, timing analysis, lint, and CDC tools.
Robust debugging and problem-solving skills.
Role: FPGA Engineer, Industry Type: Miscellaneous, Department: Engineering - Hardware & Networks, Employment Type: Full Time, Permanent Role Category: Hardware Education UG: Graduation Not Required read more
Key Skills Skills highlighted with ‘‘ are preferred keyskills FPGAVerilogRTL Coding RTL Design