- Bachelor's / Master's degree in engineering from EEE / E&C; with expertise in RTL & FPGA Validation
- Expertise in RTL design and verification flows.
- Expertise in hardware emulation platforms and FPGA Validation.
- Expertise in emulation setup, compilation, and debugging.
- Expertise in with System Verilog and Verilog.
- Expertise in configuring emulation platform tools such as Cadence Palladium, Synopsys ZeBu, or Siemens Veloce to validate hardware designs and accelerate debugging before tape-out.
- Experience in performance analysis, debug, and resolving emulation issues.
- Debug issues, run extensive test scenarios, and ensure the emulated system accurately mirrors the final products behaviour.
- Collaborate with design and verification teams to optimize performance and reduce time-to-market for complex chip designs.