- Strong expertise in SystemVerilog and UVM
- Hands-on experience in PCIe Gen3/Gen4/Gen5/Gen6 verification
- Expertise in IP, Subsystem, and SoC-level verification
- Experience in SVA, constrained-random testing, scoreboards, and coverage closure
- Proficiency in VCS/Xcelium/Questa and Python scripting
Positive to Have: CXL, AXI, Formal Verification, and GLS.