Senior I/O Layout Engineer

Location:
Bengaluru, India

Experience:
4–12 Years Technology Nodes:
• TSMC: A14 (14Å), N2 (2nm), N3 (3nm), N5 (5nm)
• Samsung: SF2 (2nm), 4nm Role Overview We are seeking highly skilled I/O Layout Engineers with strong hands-on expertise in full-custom I/O layout design across advanced technology nodes. The ideal candidate will have experience in I/O cell development, transistor-level layout, physical verification, and PPA optimization, with a deep understanding of FinFET and GAA/nanosheet technology constraints.

Key Responsibilities
• Develop and optimize full-custom layouts for I/O cells, GPIO, bidirectional buffers, level shifters, and ESD protection circuits.
• Implement layouts for I/O drivers, receivers, high-voltage-tolerant interfaces, and power/ground I/O cells.
• Drive transistor-level floorplanning, device placement, routing, and layout optimization.
• Optimize layouts for area, parasitics, signal integrity, electromigration, and reliability.
• Ensure compliance with advanced-node foundry design rules and I/O-specific electrical constraints.
• Perform physical verification, including DRC, LVS, ERC, antenna checks, and latch-up-related checks.
• Execute parasitic extraction (PEX) and support post-layout simulation and design closure.
• Address advanced-node challenges involving restricted routing, layout-dependent effects (LDE), density rules, and device matching.
• Collaborate with circuit design, ESD, reliability, and physical verification teams to achieve tape-out readiness.




• Own block-level layout development from schematic handoff through physical verification sign-off. Required Technical Skills
• 4–12 years of hands-on experience in full-custom I/O layout design.
• Solid expertise in I/O cell layout, GPIO, I/O buffers, level shifters, and ESD structures.
• Experience with advanced technology nodes, preferably TSMC 5nm/3nm/2nm/A14 or Samsung 4nm/2nm.
• Strong understanding of FinFET and GAA/nanosheet layout methodologies, including foundry-specific design rules.
• Proficiency in Cadence Virtuoso Layout Suite.
• Hands-on experience with Siemens Calibre / Cadence Pegasus / Synopsys IC Validator or equivalent physical verification tools.
• Strong expertise in DRC/LVS debugging, parasitic extraction, and layout sign-off.
• Understanding of ESD protection, latch-up prevention, power routing, and I/O reliability requirements.
• Experience with multi-voltage-domain layout, guard rings, isolation, and noise-sensitive routing. Preferred Qualifications
• Direct layout experience on TSMC N5/N3/N2/A14 or Samsung 4nm/2nm processes.
• Experience in advanced-node I/O libraries, pad-ring integration, and I/O macro development.
• Exposure to ESD-aware layout, high-current I/O structures, and reliability verification.
• Knowledge of high-speed I/O or mixed-signal interface layout.
• Experience with complete layout ownership, physical verification closure, and tape-out.
• B.
E./B.
Tech or M.
E./M.
Tech in Electronics, Electrical Engineering, Microelectronics, or related disciplines.

📌 Senior I/O Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru