Technology Nodes:
• TSMC: A14, 2nm, 3nm, and 5nm
• Samsung: 2nm and 4nm Job Summary We are looking for experienced IO/MXS Layout Engineers with expertise in advanced semiconductor technology nodes. The candidate should have strong experience in IO and MXS layout design, physical implementation, and layout verification.
Key Responsibilities
• Develop and implement IO/MXS layouts for advanced technology nodes.
• Work on layout design, optimization, and physical verification.
• Perform DRC, LVS, and other layout verification checks.
• Debug and resolve layout-related issues to meet design and manufacturing requirements.
• Collaborate with circuit design, physical design, and verification teams.
• Ensure compliance with foundry design rules and technology-specific requirements. Required Skills
• Solid experience in IO/MXS layout design.
• Hands-on experience with advanced technology nodes from TSMC or Samsung.
• Familiarity with custom layout tools such as Cadence Virtuoso.
• Knowledge of DRC, LVS, and physical verification methodologies.
• Experience in debugging and resolving complex layout issues.
• Understanding of advanced process technology design rules.