Key Responsibilities
• Lead end-to-end Physical Design implementation from Netlist to GDSII.
• Own Floorplanning, Power Planning, Placement, CTS, Routing, STA, ECO, and Signoff activities.
• Drive timing closure.
• Resolve congestion, IR drop, EM, noise, SI, DRC, and LVS issues.
• Perform and review physical verification and signoff checks.
• Collaborate with RTL, STA, DFT, PDK, CAD, and Verification teams.
• Define implementation methodologies and improve design flows.
• Lead block/full-chip integration and tape-out activities.
• Develop and maintain Tcl/Python automation scripts.
• Provide technical guidance, reviews, and mentoring to junior engineers.