Job Title: DV Engineer - 6-8 Yrs

Location: Hyderabad

No. Of positions: 2

Experience required: 6-8 years

- Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debuggin.
- He should be an enthusiastic and a quick learner of the verification flow.

Basic Job Deliverable:

- SV / UVM Test bench development and test cases coding
- Code and Functional coverage analysis and closure
- Formal verification exposure is an added advantage
- Work with team for verification closure
- Experience with python or any other scripting language is a plus
- Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage.

Qualification:

- B.E / M.E / B.Tech / M.Tech




- Need a candidate with robust expertise in Verification methodology, environment development , test case coding and support work.
- Good at design concepts.
- Able to work independently

Must have Skills:

- System verilog
- Verilog
- UVM Methodology

Secondary skills:

- DFX
- Bus protocols AXI / APB / UART/ IJTAG
- Python or any other scripting language

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 DV Engineer (Hyderabad)
🏢 Proxelera
📍 Hyderabad