- TSMC 5nm and lower nodes custom Layout design of analog and mixed signal blocks.
- Hands on experience with hierarchical layout design including track planning, PG planning.
- Robust debugging skills with Calibre DRC, LVS and Antenna checks.
- Ability to independently handle multiple tile layout development along with PV closure.
- Exposure to PD flows and understanding of DEF/LEF handling is desired.
- Exposure to AMD TBUR and SERAS flows is desired.
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