Experience is primarily hands-on IP design, preferably with at least 4 years of substantial and sustained design ownership, including:
- Understanding specifications and converting requirements into design
- Microarchitecture and block-diagram development
- RTL development of complete IPs or substantial functional blocks
- FSM, datapath and control-logic design
- Experience with interfaces/IPs such as APB/AHB/AXI, SPI, I2C, UART, DMA, timers, WDT, GPIO, memory controllers, etc.
- Ownership from RTL design through simulation/debug, Lint/CDC and integration
- Exposure to simulation, Lint, CDC, synthesis and integration is helpful, but these should not be the candidate’s primary responsibility.
📌 Senior IP Design Engineer (Bengaluru)
🏢 HrdWyr
📍 Bengaluru
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