29 Oct
|
Creeno Solutions Private
|
Bengaluru
29 Oct
Creeno Solutions Private
Bengaluru
About the Roleonsemi is seeking a DFT Engineer to support the design and implementation of Design‑for‑Test (DFT) features for complex ASIC/SoC products across automotive and industrial applications. This role focuses on scan, ATPG, MBIST, and boundary scan, with close collaboration across design, PD, and test teams.Key ResponsibilitiesDevelop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG Implement and debug DFT logic to ensure high fault coverage and test quality Generate and analyze ATPG patterns using industry‑standard tools Support at‑speed and transition fault testing Collaborate with RTL, Physical Design, STA, and Test Engineering teams Address timing, CDC, and low‑power DFT considerations Support test coverage analysis, DFT signoff, and silicon bring‑up#LI-RT1
📌 Dft Design Engineer (Bengaluru)
🏢 Creeno Solutions Private
📍 Bengaluru