HiredNext Recruitment is managing a confidential search for a Memory Layout Engineer with a semiconductor technology organisation. The employer identity will be shared only with relevant shortlisted candidates. Location: Bengaluru. Work mode: On-site. Experience: 2–5 years preferred (solid 3–10 also considered). Role overview Work on memory-layout implementation and physical verification for advanced semiconductor designs, partnering with circuit, verification and physical-design teams. Key responsibilities - Design and implement memory layouts using industry-standard tools - Work across SRAM, ROM, DRAM, CAM and related memory architectures - Develop robust layouts with attention to performance, area, reliability and yield - Perform and debug DRC, EM/IR, routing and physical-verification issues - Work closely with circuit,



verification and physical-design teams - Support layout automation and scripting where applicable - Contribute to tapeout readiness and physical-verification closure Required skills - Hands-on experience in Memory Layout Design - Strong expertise in Cadence Virtuoso - Experience with Calibre verification tools - Strong understanding of memory architectures including SRAM, ROM, DRAM and CAM - Good knowledge of design rules, parasitic effects and physical-verification flows - Strong debugging and problem-solving skills for routing, EM/IR and DRC challenges - SKILL, TCL or Python exposure is an advantage Preferred technology exposure - TSMC: A14n, 2nm, 3nm, 5nm - Samsung: 2nm, 4nm How to apply Email CV to [email protected] with subject: HN-MLE-1028 | Memory Layout Engineer Or apply: https://hirednext.net/jobs/memory-layout-engineer-bengaluru Firm: HiredNext Recruitment only. Client / end employer not named publicly.

Pay: ₹800,000.00 - ₹1,800,000.00 per year

Work Location: In person

📌 Memory Layout Engineer (Bengaluru)
🏢 HiredNext Recruitment
📍 Bengaluru