**Summary:** Meta's silicon engineering team is building custom infrastructure silicon to power the compute demands of AI, data center, and next-generation hardware platforms. The Infra Silicon Implementation CAD team owns the physical design flows and automation that take our designs from RTL handoff through synthesis, place and route, timing closure, and physical signoff. As a Physical Design CAD engineer, you will be responsible for building and owning the flow infrastructure used daily by PD engineers across concurrent tapeout programs. This is a high-leverage role: the automation you build directly determines how quickly a chip organization converges. **Required Skills:** ASIC Engineer, Physical Design CAD Responsibilities: 1. Develop, maintain, and own stages of the digital physical design flow - synthesis, floorplanning and design planning, placement, CTS, routing, extraction, timing ECO, and STA signoff 2. Build and extend flow automation in Python and Tcl, integrated with Meta's internal build, job-scheduling, and continuous integration infrastructure 3. Partner with PD engineers and design leads to debug flow and Quality of Release (QoR) issues on active tapeout programs, and convert recurring workarounds into supported flow features 4. Qualify and integrate commercial EDA tools, drive issues to resolution with vendor application-engineering teams, and manage tool version migrations across programs 5. Build constraint and netlist validation capability so design-intent errors are caught in-flow rather than at sign-off 6. Develop QoR tracking, metrics, and dashboards that give design teams and program leadership visibility into convergence across blocks and subsystems 7. Write and maintain user-facing flow documentation and training, and support designers as part of a shared on-call rotation 8.



Collaborate with external design partners and foundry or ASIC vendors on flow alignment and design handoff criteria **Minimum Qualifications:** Minimum Qualifications: 9. Bachelor's or Master's degree in Electrical or Electronics Engineering, Computer Engineering, and/or equivalent practical experience 10. 2+ years of experience in either ASIC physical design or CAD, including hands-on work with automation, flow development, drafting methodologies, solutions, and/or hands-on work with placement, clock tree synthesis, routing, and timing closure 11. Experience with digital physical design implementation on advanced process nodes, including synthesis, place and route, and timing closure 12. Hands-on experience with industry physical design tools, such as Fusion Compiler, Genus, Innovus, PrimeTime, Tempus, or StarRC 13. Proficiency in Tcl and Python for EDA flow development and automation 14. Experience debugging flow, timing, or physical verification issues on a production tapeout 15. Experience with version control and team-oriented code review **Preferred Qualifications:** Preferred Qualifications: 16. Experience working across geographically distributed teams and with external design partners 17. Experience with power integrity and EM/IR analysis, and/or physical verification and logic equivalence sign-off 18. Experience with timing constraint development and validation methodology, including SDC generation and constraint checking 19. Experience building or owning a production CAD or physical design flow used by multiple design teams 20. Experience building data pipelines or dashboards for design metrics and QoE analysis 21. Experience with compute and license capacity management for large EDA workloads 22. Experience applying AI or LLM-based tooling to engineering workflows 23. Experience with hierarchical design planning and block-level partitioning on large SoCs **Industry:** Internet

📌 ASIC Engineer, Physical Design CAD (Bengaluru)
🏢 Meta
📍 Bengaluru