Role Summary The RTL Design Engineer will independently develop synthesizable RTL for assigned blocks under the guidance of the Technical Lead while collaborating with verification and implementation teams.
Responsibilities
- Develop synthesizable Verilog/System Verilog RTL.
- Understand design specifications and implement block-level functionality.
- Perform RTL simulations and debug failures.
- Resolve
- Lint issues
- CDC violations
- RDC violations
- Support synthesis and timing closure activities.
- Participate in design reviews.
- Prepare RTL documentation.
- Work closely with DV, STA and PD engineers.
Required Skills
- 4–6 years RTL Design experience
- Solid Verilog/System Verilog coding
- Digital Design fundamentals
- FSM
- Counters
- FIFOs
- Arbitration logic
- State Machines
- Pipeline design
- Reset handling
- Clock gating
- CDC basics
- RDC basics
- Lint analysis
- Simulation debugging
- Synthesis awareness
- Familiarity with VCS/Xcelium and Verdi
- Good debugging and analytical skills